Verilog-Based Simulation of UWB Radar Data Acquisition for Pulsed-Radar Signal Processing on FPGA (Military Radar)

Abstract

This work reports an RTL-level study of a pulsed-radar data-acquisition chain designed entirely in Verilog. The project was approached in two parts. First, a dual-channel front end was created to reproduce 12-bit ADC output and to apply a reduced-rate sampling method before sending the data into independent FIFO buffers. This allowed us to examine how the system reacts when the PRF is pushed high, particularly in terms of timing, throughput, and the way the buffers fill and empty. In the second part, the model was expanded into a real-time processing path similar to what would run on an FPGA, and it was tested at roughly 9,000 pulses per second on each channel. The processing stage uses Verilog modules for pulse averaging, window shaping, and simple interference handling, and these modules were validated using ModelSim. MATLAB was used only to review the captured signals and verify SNR and latency results. The study focuses on decisions that influence real hardware—buffer sizes, clock-domain handling, and timing margins—rather than idealized assumptions. The design can function with low latency and without data loss, according to the simulation results, which makes it appropriate for UWB radar systems that require consistent performance in noisy military scenarios.