Designing High Speed 8bit vedic multiplier using Brent Kung Parallel Prefix Adder

Abstract

The need for high-speed arithmetic operations in modern digital systems, particularly in processors and signal processing units, has led to the exploration of efficient multiplier architectures. This paper presents the design and implementation of a high-speed 8-bit Vedic multiplier integrated with a Brent-Kung parallel prefix adder for optimized performance. Vedic multiplication, derived from ancient Indian mathematics, offers significant advantages in terms of speed and regularity due to its recursive Urdhva Tiryagbhyam (vertical and crosswise) algorithm. To further enhance computation speed, the final addition stage of partial products employs the BrentKung adder — a logarithmic time complexity adder known for its minimal logic depth and reduced fan-out compared to other parallel prefix adders. The proposed architecture is modeled using Verilog HDL and synthesized  using Xilinx Vivado. Comparative analysis demonstrates that the combination of Vedic multiplication and Brent-Kung addition achieves lower delay, reduced area, and improved power efficiency when compared to traditional array multipliers and ripple carry adder-based implementations. The results validate that the design is wellsuited for high-speed applications in embedded systems, digital signal processors, and cryptographic hardware. A high-speed 8-bit multiplier architecture based on Vedic mathematics is  presented, utilizing the Urdhva Tiryagbhyam sutra for efficient partial product generation. To further accelerate the computation process, the final addition of partial products is performed using the Brent-Kung parallel prefix adder, known for its logarithmic delay and minimal fan-out, making it suitable for high-speed arithmetic circuits. The integration of Vedic multiplication with the Brent-Kung adder significantly reduces propagation delay, area, and power consumption when compared to conventional multiplier architectures employing ripple carry adders or carry-save adders. The proposed design is described in Verilog HDL and synthesized using Xilinx Vivado for performance evaluation. Simulation results demonstrate improved speed and resource utilization, highlighting the proposed architecture’s suitability for realtime and embedded signal processing applications.