Verilog-Based Simulation of Phase Estimation Block for Range-Doppler Processing in SAR/Radar Imaging Systems

Abstract

This work is basically about trying to simulate the range-Doppler part of a SAR processor on an FPGA. The idea is to see how the core blocks of a SAR imaging chain behave when pushed toward real-time speeds. I split the whole thing into two parts so it’s easier to build and test step by step. In Phase 1, a Verilog-based simulation of the phase estimation and FFT blocks is developed, which are essential components of the SAR range-Doppler algorithm. The objective is to model the frequency-domain transformation and accurately estimate the phase information of received echoes, enabling the analysis of phase accuracy and resolution performance critical to high-precision SAR imaging. In Phase 2, the full range-Doppler processing pipeline is constructed in Register Transfer Level (RTL), including modules for range compression (convolution), Doppler FFT, and matched filtering. The RTL designs are validated using standard SAR raw datasets in MATLAB, with performance metrics such as image resolution, peak sidelobe ratio (PSLR), and integrated sidelobe ratio (ISLR) being evaluated. The project builds upon recent advancements in FPGA-accelerated SAR imaging architectures that aim to meet the low-latency, high-throughput demands of airborne and spaceborne radar platforms. The integration of Verilog simulation with MATLAB-based image reconstruction ensures functional correctness while enabling resolution benchmarking. This work demonstrates the feasibility and effectiveness of real-time SAR range-Doppler implementation on FPGA platforms for defense, remote sensing, and surveillance applications.