AN EFFICIENT MULTIBIT UPSET DETECTION AND CORRECTION IN 64-BIT SRAM BASED FPGA MEMORY USING DECIMAL MATRIX CODE

Abstract

In order to safeguard memory against radiation, this study lays forth an effective method for correcting Multiple Bit Upsets (MBUs). The main problem with the old method of protecting memories from MBUs—which included using several sophisticated error correction codes— was the increased redundant memory expense.To guarantee memory dependability, this article suggested a 64-bit Matrix Code. In order to find and fix additional mistakes, the suggested protection code used a process. The results demonstrated a degree of protection against huge MBUs in memory for the suggested method. One of the most significant issues with the dependability of memory in a radiation environment is transient multiple bit upsets (MBUs). To repair memory errors, the suggested approach makes use of a 64-bit matrix. More complicated error correction codes (ECCs) are often used to safeguard memory against MBUs corrupting data, but their primary drawback is the increased delay overhead they entail. There have been recent proposals for memory protection using matrix codes (MCs) based on Hamming codes. The fact that they are error correction codes twice is the biggest problem, and not every situation benefits from the expanded mistake correction capabilities. Also, without affecting the overall encoding and decoding procedures, erasure codes are suggested as a means to lessen the area overhead of additional circuits. These days, several error detection and repair techniques are used to secure memory bits with protection codes, which is essential for ensuring a high degree of dependability. More redundant bits are needed to ensure improved memory dependability, which is the only downside of the present MC. In order to guarantee stability in the face of multiple bit upset, remove unnecessary bits, and rectify more errors than the present system, the suggested approach employed matrix coding.