Sub-threshold circuit standby and active energy optimization at the same time is possible thanks to this technique

Abstract

Leakage current increases dramatically when CMOS circuits are downscaled in terms of feature size and threshold voltage. Consequently, decreasing leakage power is a critical design issue as technology goes up, in both active and standby modes. For 22 nm sub-threshold CMOS circuits, this work proposes a combined active and standby energy optimization mechanism. When it comes to active energy consumption per cycle, a dual threshold voltage design is the first option to be explored. For non-critical routes, slack-based evolutionary algorithms can assign reverse body bias for least active energy per cycle and highest frequency at optimal supply voltage. In this study, a lower triangular encoder for IEEE 802.11n wireless LAN is developed with a block length of 648 and a coding rate that is half as fast. At 301.433MHz, the LDPC encoder's hardware implementation runs at 12.12 Gbps.