AN EFFICIENT MULTIBIT UPSET DETECTION AND CORRECTION IN 64-BIT SRAM BASED FPGA MEMORY USING DECIMAL MATRIX CODE

Abstract

In order to safeguard memory against radiation damage, this work provides a low-cost method of correcting Multiple Bit Upsets (MBUs). Many complicated error correction codes (ECCs) have been employed in the past to safeguard memories against MBUs, but the main problem is greater redundant memory costs.In this study, we suggest using 64-bit Matrix Code to guarantee memory's dependability. In order to catch more mistakes and fix them, the suggested protection code made use of a mechanism to do so. The results demonstrated that the suggested technique offers some security against memory-intensive MBUs of significant size. The reliability of memory in a radiation environment is severely compromised by transient multiple bit upsets (MBUs). The suggested technique uses a 64-bit matrix for memory error correction. Complex error correction codes (ECCs) are frequently employed to safeguard memory against MBUs that might cause data corruption, but the primary issue is that they would demand greater delay overhead. Recently, matrix codes (MCs) based on Hamming codes has been suggested for memory protection. The primary difficulty is that these codes are double error correction codes, and their error correction capabilities are not always improved. In addition, erasure codes are suggested to cut down on the space overhead of additional circuits without affecting the overall encoding and decoding operations in any way. Modern error correction techniques need the use of protection codes to keep memory bits secure. There are techniques of detection and rectification in use. The only real problem with the current MC is that more redundant bits are needed to maintain the same level of memory dependability. In order to guarantee dependability in the face of multiple bit upset, the suggested method made use of a matrix code to cut down on redundancy and rectify more errors than the current approach.