Design Of ALU Using Ternary Logic

Abstract

This paper presents the design and implementation of an Arithmetic Logic Unit (ALU) based on ternary logic using Verilog HDL. Unlike traditional binary systems that use two logic states (0 and 1), ternary logic incorporates a third logic level, typically represented as −1, 0, and +1 or 0, 1, and 2, enabling more compact and efficient digital designs. By leveraging ternary logic, the proposed ALU performs essential arithmetic and logic operations such as addition, subtraction, comparison, inversion, and various logic gates using ternary inputs and outputs. The design is modeled and simulated using Xilinx Vivado software, and the results demonstrate reduced gate complexity and improved performance potential in certain cases compared to binary ALUs.

The ALU is the core of any processing unit, responsible for executing both arithmetic and logical operations. In conventional binary logic, implementing multiple functions often leads to increased circuit complexity and power consumption. Ternary logic offers a compact alternative by reducing the number of interconnections and gates required for logic synthesis. In this work, fundamental ternary components such as ternary half adder, half subtractor, comparator, ternary inverter, and various ternary logic gates were individually designed and integrated to form a functional ternary ALU. Each module was verified using Verilog testbenches to ensure correctness in all possible ternary input combinations. Simulation results confirm accurate functionality and demonstrate the feasibility of ternary logic for future VLSI systems emphasizing power efficiency and high circuit density.