DESIGN OF HIGH PERFORMANCE DYNAMICALLY TRUNCATED APPROXIMATE MULTIPLIER FOR VLSI APPLICATIONS

Abstract

Multipliers serve as integral arithmetic functional units across various applications, often necessitating numerous multiplications that contribute significantly to power consumption. To mitigate this challenge, the adoption of approximate multipliers has emerged as a promising strategy in applications tolerant to errors, offering a trade-off between accuracy, energy efficiency, and performance. In this study, we present a novel approach comprising an approximate 4-2 compressor of high accuracy, coupled with an adjustable approximate multiplier capable of dynamically truncating partial products to accommodate variable accuracy requirements. Furthermore, we introduce a straightforward error compensation circuit to minimize error distances. Our proposed approximate multiplier offers runtime adjustment of accuracy and power consumption tailored to user specifications. Experimental findings showcase notable reductions in both delay and average power consumption of the adjustable approximate multiplier—27% and 40.33% (up to 72%) respectively—compared to traditional Wallace tree multipliers. Moreover, we illustrate the adaptability and versatility of our proposed multiplier within convolutional neural networks (CNNs), demonstrating its efficacy in meeting diverse requirements across different network layers. This multifaceted approach not only enhances energy efficiency and performance but also underscores the flexibility and applicability of approximate multiplication techniques in real-world applications.