AN EFFICIENT MULTIBIT UPSET DETECTION AND CORRECTION IN 64-BIT SRAM BASED FPGA MEMORY USING DECIMAL MATRIX CODE

Abstract

In order to safeguard memory against radiation, this study lays forth an effective method for correcting Multiple Bit Upsets (MBUs). There has been a significant increase in duplicate memory overhead due to the earlier employment of several complicated error correction codes (ECCs) to safeguard memories from MBUs.The study suggests using a 64-bit Matrix Code to guarantee memory stability. In order to find and fix additional mistakes, the suggested protection code used a process. The results shown that the suggested method offers some defense against memory-bound big MBUs. One of the most significant issues with the dependability of memory in a radiation environment is transient multiple bit upsets (MBUs). We use a 64-bit matrix for memory error correction in the suggested technique. More complicated error correction codes (ECCs) are often used to safeguard memory against MBUs corrupting data, but their primary drawback is the increased delay overhead they entail. Memory protection matrix codes (MCs) derived from Hamming codes have recently been suggested. The fact that they are error correction codes twice is the biggest problem, and not every situation benefits from the expanded mistake correction capabilities. In addition, erasure codes are suggested as a means to lessen the space overhead of additional circuits without interfering with the overall encoding and decoding procedures. These days, protecting memory bits with codes is essential for maintaining a decent degree of dependability; to achieve this goal, several mistakes approaches for detection and correction are being used. The current MC has one major flaw: in order to keep memory reliability high, additional redundant bits are needed. Matrix coding increases dependability in the event of many bit upsets, reduces unnecessary bits, and corrects more errors than the current approach.